This invention relates to reducing gate oxide thinning at the field edge of complimentary metal oxide semiconductor (CMOS) devices and, more particularly, to reducing field edge thinning in peripheral devices.
Some CMOS devices are fabricated in such a way that a thin gate oxide and a thick gate oxide are grown on the device. In some processes for fabricating these peripheral CMOS devices, the thin gate oxide devices are sometimes stripped with a wet oxide etch prior to gate oxidation. In other processes, the thick gate oxide devices are sometimes stripped with a wet oxide etch prior to gate oxidation. When a device is stripped with a wet oxide etch, the silicon corners at the field edges may be exposed. This results in increased gate oxide thinning at the field edges (e.g., at the exposed corners). This increased thinning may lead to undesirable variability in the electrical parameters of the peripheral devices.
For example, the increased thinning at the field edges may cause a MOSFET (metal oxide semiconductor field effect transistor) to break down at the corners due to the non-uniformity of the gate oxide. This results in what is sometimes called a threshold kink. That is, a MOSFET may turn on closer to the device's field edges before the rest of the device turns on. When enough voltage is applied to the rest of the gate, the rest of the device may turn on. In essence, this results in two devices in parallel. This variability and other factors may lead to degradation in functionality, yield, and reliability in these devices.
It would therefore be desirable to be able to provide fabrication processes that reduce field edge thinning in peripheral devices.